A warning occurs in the Timing Analyzer when using the Clock Output Division feature of the Clock Control Intel® FPGA IP core

Description

The following warning appears in the Timing Analyzer when using the Clock Output Division feature of the Clock Control Intel® FPGA IP core:

Ignored filter at <name>_intelclkctrl_<unique identifier>.sdc(293): |intelclkctrl_0|clkdiv_inst|clock_div1/2/4 could not be matched with a pin

The warning might occur when either the clock_div1x, clock_div2x, or clock_div4x are enabled in the IP core but are not physically connected in your design. 

Resolution

This warning can be safely ignored if the clock is intentionally unconnnected.