<your_ip>.regmap file not generated when using the Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile CPRI PHY IP Core is generated?

Description

UG-20160 | 2020.06.29 and earlier versions indicate that the file <your_ip>.regmap will be created when generating the Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile CPRI PHY IP Core. This is incorrect. The file <your_ip>.regmap is not generated.

Resolution

This mistake has been removed from the IP Core Generated Files table, updated for version 20.2 of the Intel® Quartus® Prime Design Suite.