*** Fatal Error: Access Violation, Module: quartus_map.exe, Stack Trace: TIS_PLL_UTIL::get_normal_input_compensation_delay 0x48 (tsm_tis)

Description

This error may occur in the Quartus® II software version 9.0, if Physical Synthesis optimizations are enabled for your project and your design contains a PLL with an illegal reference clock connection.

To work around this problem, follow these steps:

1. Disable Physical Synthesis optimizations for your project and recompile your design.
2. Examine your Analysis & Synthesis report to identify any PLLs with illegal reference clock connections.
3. Fix these connectivity errors and recompile your design.
4. After you have fixed the illegal connections, you can enable Physical Synthesis optimizations again for your Quartus II project.

This problem is scheduled to be fixed in a future version of the Quartus II software.