# ** Error: (vsim-3033) <Verilog HDL file name>(): Instantiation of 'LCELL' failed. The design unit was not found.

Description

You may see this error when compiling your RTL in the ModelSim simulator if you instantiate an LCELL in uppercase in your Verilog HDL design file.

Resolution

To avoid this error, instantiate LCELL in lowercase in your Verilog HDL design file.