New ContributorCan someone suggest a basic HPS project with PIO for LED control.
Need the complete flow of building the project from scratch.
New ContributorWe are using Quartus 26.1 for all these activites.
New ContributorThank you for the details. Now iam able to compile the desigsn and the .sof is getting generated.
Now need to add the bootlaoder .hex fille to generate the .pof programming file.
Can you let me know from where can i get the boot loader file and the steps to add it to the FPGA programming file.
From where does the boot loader run? From QSPI flash or do we need to create an internal RAM in FPGA for the HPS?
New ContributorStratix® 10 devices use a Secure Device Manager (SDM) to control both FPGA configuration and HPS boot. As part of this architecture, .pof files are not used. Instead, the device is programmed using .rbf (Raw Binary File) images, which can includes the HPS bootloader.
You may get the precompiled first stage bootloader (FSBL) .hex from here:
https://releases.rocketboards.org/2026.04/emmc/s10_htile_emmc/u-boot-spl-dtb.hex
This bootloader is generated as part of the Yocto-based GSRD build flow. For more details on how it is built, refer to: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/
If you prefer to build the bootloader manually, you can follow this guide: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/boot-examples/ug-linux-boot-s10-soc/
The steps to include the bootloader into the .sof are documented here: https://docs.altera.com/r/docs/683847/26.1/stratix-10-soc-fpga-boot-user-guide/creating-the-configuration-files
Example, if you have a HPS boot first design and configures via JTAG:
quartus_pfg -c design.sof design.rbf -o hps_path=fsbl.hex -o hps=onFor QSPI boot, you can follow this guide: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#boot-from-qspi
A detailed description of the boot flow is available here: https://docs.altera.com/r/docs/683847/26.1/stratix-10-soc-fpga-boot-user-guide/boot-flow-overview
At a high level:
1. SDM reads the configuration image (e.g., from QSPI, SD, EMMC, or JTAG)
2. SDM loads the FSBL into HPS on-chip RAM
3. HPS starts executing the FSBL
4. FSBL initializes DDR and loads the next-stage bootloader (SSBL / U-Boot)
For SDM-based devices:
No additional RAM for the HPS needs to be added in the FPGA fabric
Once the RBF is loaded, the FSBL runs from HPS OCRAM, and the rest of the boot sequence proceeds from there.
New ContributorOur baord is a custom board with an 8GB eMMC. Option is provided to boot from JTAG and QSPI with MSEL switches.
We could generate the .sof file by following the steps discussed earlier.
We downloaded the precompiled first stage bootloader (FSBL) .hex as suggested earlier.
Generated the .JIC file with the .sof and FSBL included in it and programmed the QSPI through JTAG.
A FAT32 USB drive is plugged in to the USB port with second stage bootloader.bin and kernal.bin.
Then we put MEL pins to boot from QSPI. Our expectation was that the HSP should boot with the linux in the USB drive. But we are getting this error message in the UART0 port.
U-Boot SPL 2022.10 (Mar 20 2023 - 03:03:15 +0000)
Reset state: Cold
MPU 1200000 kHz
L3 main 400000 kHz
Main VCO 2400000 kHz
Per VCO 2000000 kHz
EOSC1 25000 kHz
HPS MMC 20000 kHz
UART 100000 kHz
DDR: Warning: DRAM size from device tree mismatch with hardware.
DDR: 4096 MiB
QSPI: Reference clock at 400000 kHz
WDT: Started watchdog@ffd00200 with servicing (10s timeout)
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.itb, err - -1
Trying to boot from SPI
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Can you suggest what could be the issue.
Also can you let us know the steps to install the linux in eMMC from the USB drive so that it can boot into linux from eMMC.
New Contributorthank you for the feedback.
You are right, i cant add any attachment too.
I will feedback that to the team.
I recommend comparing your .qsf file against the version provided in the zip file here:
For the DDR4 pins, the user may also need to manually assign the corresponding pins in the .qsf file.
If you are using both HPS and EMIF, I recommend starting from the example here as a baseline:
New ContributorRegarding the attachment, I have rechecked it. Please kindly rename the .rpt file to .txt before uploading.
I can attach a zip file.
New ContributorFitter report attached.
Also can you help me to get started with the GSRD. How to generate the Quartus project from the GSRD. Coun't find any Quartus project file in it.
New ContributorHi Sajeev_antony,
There is a QSF setting that promotes specific warnings to errors.
# Promote pins without location assignments to errors
set_global_assignment -name PROMOTE_WARNING_TO_ERROR 12677If this option is enabled, all top-level pins are required to have complete assignments, including:
For a quick initial test, I would suggest disabling this setting to allow the build to proceed without being blocked by these checks.
If you would like to identify the exact pin(s) causing the issue, could you please share the full fitter report?
Thank you.
Best regards,
shun jing.
New ContributorHow to upload report files. it dosnot allow me to upload the file.
Iam using HPS and hard EMI for DDR4. Do i have to assign pin for DRR4 or will the quatrus auto assigne it.
New ContributorOn compiling the Quartus project with Stratix 10 HPS, iam getting this warning and the programming file is not getting generated.
Critical Warning(25196): A programming file will not be generated because the assembler identified user pins missing pin location assignments. Refer to the I/O Assignment Warnings table in the fitter report for a list of unassigned pins. You can assign these pins in the Pin Planner tool and recompile to allow programming file generation to pass.
Critical Warning(25207): A programming file will not be generated because the assembler identified some pins have missing I/O Standard assignments. Refer to the I/O Assignment Warnings table in the fitter report for details.
But in the fillter report there are no unassigned pins.
Any idea what could be the issue.
ContributorHi Sajeev_antony,
Please refer to the following resources:
https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/
https://altera-fpga.github.io/rel-24.3/embedded-designs/stratix-10/sx/soc/emmc/ug-emmc-s10sx-soc/
I hope that helps.
Sue
New ContributorAfter selecting the HPS peripheral in the auto place IP, the HPS pins come up in the top level instantiation.
These HPS pins eg. SDMMC, USB etc which are part of HPS show up in the FPGA pin planner. But not able to assigne any location to it. How do the locations get assigned to these dedicated HPS pins.
Occasional ContributorThey got assigned based on the PINMUX selection where the user selects the peripherals to be enabled. Quartus will automatically, picked the IOs and assigned them respectively. As per the spec (if i am not mistaken), you can't assign HPS dedicated pin locations in pin planner because the package balls are fixed per device. You can only choose the function and mux as i explained above in the HPS Platform designer. Pin planner is basically for reviews only. Then, it will be translated to a handoff (part of the bitstream) for the HPS FSBL to then configure the PINMUX/IO manager.
If you are looking for the GPIO for LEDs, they are as followed below. If you are using the GHRD official design, you can then, control the LEDs output through this IOs.
