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SJeon37's avatar
SJeon37
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6 years ago

MAX 10 ADC Sequencer Core Command Register Setting

Hi,​ I am testing the ADC in FPGA MAX 10 (10M50DAF484C6GES). With reference to the example code below, it seems that the adc operation does not stop even if the RUN bit is set to 0. I would like t...
EngWei_O_Intel's avatar
EngWei_O_Intel
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6 years ago

Hi SangCheol

By looking at the sequencer design, seems not sufficient for me to articulate the issue. Do you mind to share with me the entire design? Are you testing it on a simulator or the actual hardware?

Thanks.

Eng Wei

EngWei_O_Intel's avatar
EngWei_O_Intel
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6 years ago

Hi SangCheol

We do not receive any response from you to the previous question that we need more details on the issue you are facing. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei