how to use separated the FPGA configuration and HPS booting?

Hi,

Can you quick clarify the steps to disabled the Early IO Release?:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-fpga-early-io-release.pdf

i have no questions on early IO release, I unchecked this option in both HPS EMIF setting of platform designer and the device and pin options of Quartus, as i showed in below images with red highlighted.

my question is just to double confirm with you, per my test, the waiting loop is not in boot ROM and also not in SPL. So for my application, I need to add a wait loop in SPL by myself to let it wait until the FPGA config done, then the booting will jump out from the wait loop and go ahead and we need not trigger the HPS reset again after FPGA config done.

thanks.

Hi,

Okay, can you see the below logs, below logs shown that the first two initial logs where it needs an FPGA configuration done before booting the SPL, after the two initial logs, the FPGA is programmed successfully using Quartus Programmer, you can see the U-boot SPL loading and go into U-boot user mode, did you see this behavior? Does this fits your design requirement?:

U-Boot SPL 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)

FPGA: Checking FPGA configuration setting ...

FPGA: Checking FPGA configuration setting ...

FPGA: Checking FPGA configuration setting ...

WDT: Started watchdog@ffd00300 with servicing (10s timeout)

Trying to boot from SPI

QSPI: Invalid input arguments txlen 64

SPL: failed to boot from all boot devices

### ERROR ### Please RESET the board ###

U-Boot SPL 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)

FPGA: Checking FPGA configuration setting ...

FPGA: Checking FPGA configuration setting ...

FPGA: Checking FPGA configuration setting ...

WDT: Started watchdog@ffd00300 with servicing (10s timeout)

Trying to boot from SPI

QSPI: Invalid input arguments txlen 64

SPL: failed to boot from all boot devices

### ERROR ### Please RESET the board ###

U-Boot SPL 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)

U-Boot SPL 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)

DDRCAL: Success

DDRCAL: Scrubbing ECC RAM (1024 MiB).

DDRCAL: SDRAM-ECC initialized success with 146 ms

WDT: Started watchdog@ffd00300 with servicing (10s timeout)

Trying to boot from SPI

U-Boot 2022.04-21230-gfcf317324c-dirty (Oct 20 2022 - 05:12:31 +0800)socfpga_arria10

CPU: Altera SoCFPGA Arria 10

BOOT: QSPI Flash (1.8V)

Model: Altera SOCFPGA Arria 10

DRAM: 1 GiB

Core: 69 devices, 16 uclasses, devicetree: separate

WDT: Started watchdog@ffd00300 with servicing (10s timeout)

Loading Environment from SPIFlash... SF: Detected mt25qu01g with page size 256 Bytes, erase size 4 KiB, total 128 MiB

*** Warning - bad CRC, using default environment

In: serial

Out: serial

Err: serial

Model: Altera SOCFPGA Arria 10

Net:

Warning: ethernet@ff800000 (eth0) using random MAC address - 52:6c:4d:8d:5c:15

eth0: ethernet@ff800000

Hit any key to stop autoboot: 0

=>

yes, we received similar information as yours, i attached mine as below.

per our understanding, the Boot ROM print nothing, from the first line of printed message, the process has already entered into the SPL step.

and the content of first line also indicates the U-Boot SPL version, i don't think the Boot ROM knows this.

you can see the bold and italic message, which we added into SPL code to print more reference information for us, it was printed from the 2nd line.

U-Boot SPL 2021.04 (May 24 2023 - 11:38:08 +0800)
In early user mode!
FPGA: Checking FPGA configuration setting ...
not In mode!
2nd time not in user mode
FPGA: Checking FPGA configuration setting ...
WDT: Started with servicing (10s timeout)
Trying to boot from SPI
QSPI: Invalid input arguments txlen 64
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

U-Boot SPL 2021.04 (May 24 2023 - 11:38:08 +0800)
In user mode!
not In mode!
regular boot not valid

U-Boot SPL 2021.04 (May 24 2023 - 11:38:08 +0800)
In user mode!
not In mode!
regular boot valid
DDRCAL: Success
WDT: Started with servicing (10s timeout)
Trying to boot from SPI

U-Boot 2021.04 (May 23 2023 - 18:00:07 +0800)socfpga_arria10

CPU: Altera SoCFPGA Arria 10
BOOT: QSPI Flash (1.8V)
Model: SOCFPGA Arria10 Dev Kit
DRAM: 1 GiB
WDT: Started with servicing (10s timeout)
Loading Environment from SPIFlash... SF: Detected n25q00a with page size 256 Bytes, erase size 4 KiB, total 128 MiB
OK
In: serial
Out: serial
Err: serial
Model: SOCFPGA Arria10 Dev Kit

Hi,

Okay lets go back to your final question, which you mentioned that you "need not reset the HPS again after FPGA config is done" do you mean this on first time boot or at any time after the FPGA config/re-config will be initiate?

Again, the feature for boot HPS from FPGA is not really supported in our latest U-boot. Additionally, it takes time to program the FPGA first, as the FPGA need to be configured first, so that's one of the main cons on doing boot HPS from FPGA. We don't really recommend it.

If you need to have the HPS state the way it is and have interchangeable FPGA file, you can just do the normal booting for A10 QSPI, then do a TFTP in U-boot mode to just update/change the FPGA.itb file, plus you may more flexibility in U-boot:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Arria_10_SoC_45_Boot_from_QSPI

A10 Boot User Guide on Boot ROM:

https://www.intel.com/content/www/us/en/docs/programmable/683735/current/boot-rom-flow.html

Hi,

Just checking if you have further questions.

I have no more questions on this topic, pls close this case and very thanks your strong support these days!

Hi,

I’m glad that your question has been addressed and thanks for your patience on the response time from my side, I appreciate that. I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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