ContributorDe10 HPS issue with FPGA interval timer IP
Hi,
I'm now using the interval timer ip on HPS, I set the ip as general purposed timer.
The timer is set to 100 ms and there is a timer_palus link to my fpga led[1]
The setting is as shown:
And it was linked to fpga only AXI bridge and Avalon mm bridge.
I called the timer as shown using C:
Then I charged the timer by following orders:
*(Timer+1) = 0b1010 //Stop-1 Start-0 count -1 ITO-0
*(TImer+2) = 0x10& 0xFFFF;
*(Timer+3) = (0x10>>16)& 0xFFFF;
*(Timer+ 1) = 0b0110; //Stop-0 Start -1 count -1 ITO - 0
That should start the timer.
And I set a while loop to wait for the LED[1] to bilink for it is linked to the timeout export.
But nothing happend.
And when I want to read the *(Timer) status the TO bit is always 1 even if I set it to 0.
So my questions are:
1. What happened? Why the timer status of TO is always 1?
2.Why the led[1] didn't blink?
3. What should I do to fix it?
4. By setting the period register, ex. = 10, is that mean the timer was set to 10*100 ms?In another word, if the timer is fixed period, is that mean timer is set to 100 ms?
In case my top level file is wrong I attached my top level file, there is only one line related to the timer:
assign LEDR[1]=timer_export or something.
reguards.
