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GBraj's avatar
GBraj
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3 years ago
Solved

Arria 10 SoC FPGA Remote update via HPS/linux

Hello everybody,

we are using an Intel Arria 10 SX with HPS on a custom board (10AS057K4F40E3SG with Quartus Pro 22.4). The boot flow is as specified on Rocketboards website (https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 we modified relevant handoffs files and device trees according to board devices and HPS configurations.

Boot is working: we are using boot from SD, with early I/O release to reduce configuration time, keeping the core rbf and the peripherals rbf in the same .itb file, applying the first in the SPL and the second in uboot.

Now we would like to get a "remote FPGA update" feature without using the partial reconfiguration, having a full FPGA reconfiguration at every reboot. We know that HPS DDR3 relies on FPGA configuration so a full reconfiguration via Linux without reboot is not possible, but reboot is fine for our purposes. Power cycle the board is not.

Which is the best practice to follow? Our idea is to modify via SSH/TFTP the FIT image on the FAT partition (.itb) file and then issue a reboot command via Linux without having a power cycle of the board.

This way seems to not working as intended since at reboot the SPL sees that the FPGA is already configured (but with the old image) and it does not start the FPGA configuration. Is there a way to force it via SPL/uboot?

I hope I made myself clear, otherwise please ask me further details.

Thanks in advance.

  • Hi GBraj,


    Double config can solve the some issue related DDR issue in A10. So it will be required.


    Thanks.

    Regards,

    Aik Eu


19 Replies

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi GBraj,


    It looks like it is programming the same content again fom the code itself...

    I do not understand why but anyway does the changes works on your side after linux issues reboot command?


    Thanks.

    Regards,

    Aik Eu


  • GBraj's avatar
    GBraj
    Icon for New Contributor rankNew Contributor

    Hi Aik,

    now the changes are working as intended: a full reprogram (periph+core) of the FPGA is triggered on every reboot command by linux and also with the HPS cold reset button. Probably a more "elegant" solution would be an ifdef clause linked to a certain defconfig during the build stage of U-boot, in order to keep the compatibility with other boot sources (EPCQ/etc)...but it works.

    About the double programming of peripherals, I've found some references in the official source code: https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/arch/arm/mach-socfpga/misc_arria10.c#L142-L157

    Could you please investigate internally with your colleagues if double periph config is needed on Arria 10 SoC?

    Regards.

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi GBraj,


    Sure I will try to check from the team.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi GBraj,


    Double config can solve the some issue related DDR issue in A10. So it will be required.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor

    Hi GBraj,


    I am closing this thread for now.


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


    Thanks.

    Regards,

    Aik Eu