Agilex 5E - PCIE PERST# pin - failing compilation

Thank you both for your reply. 

I have carefully placed the PCIe RX/TX pins and used the corresponding p0_pin_perst_n_i and p0_pin_perst_n_i_1, but I might have made wrong connections in the QSYS. I have copied the Altera PCIe_subsys, it is then connected to pcie_clk_rst_subsys, pcie_gts_rst (for the system PLLs on the side of the PCIe), the 100 MHz clk reset, the 250 MHz clk reset which are synchronized in the top_wrapper.sv in the example design and are now synced on my top. Are all these needed? The wrapper contains also rst_ctrl. It seems to me that this is the place were something might get tangled because I have not connected the perst_n pins to anything else, but the corresponding inputs in the pcie_subsys 

Hi,

The error message points to your pcie_perst_n.

Please make sure you don't use this pin for other purpose in your design. Then confirm the pin location and voltage in your qsf. Below are the settings from Agilex5 Modular Dev Kit FYR. 

set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to p0_pin_perst_n_i_reset_n
set_instance_assignment -name WEAK_PULL_DOWN ON -to p0_pin_perst_n_i_reset_n

Regards,

Rong

Hi eharalanova​,

I would suggestion you to,

Check the Critical Link MitySom Dev Kit board schematic for the the Pin and IO 
Make sure have the pin assign in the correct bank and correct voltage.
Ex. Altera Agilex 5 Premium Devkit  using 3.3v for PERST.

Try to refer to the Critical Link guide on PCIe example design 

https://support.criticallink.com/redmine/projects/mitysom_a5/wiki/Mitysom-a5e-pcie-gen3x4-ep

If you have more details share here with us.