Accessing FPGA registers from u-boot.

Thanks for replying.

The Cyclone V design is fully functional in linux. Although it took way too long to get a working kernel configuration, device tree description, and fpga image. I finally managed to do it a couple of weeks ago.

The NVMe performs fine. Copying large files to a RAM drive yields about 90MB/s read speed and copying large files from RAM drive to the NVMe yields about 50 MB/s write speed.

I'm using u-boot-socfpga 2020.10 and will switch to 2021.04 when it becomes available as there are nvme enhancements that may help.

I have spent about a week digging into the u-boot issue and the problem appears to be device-tree and u-boot related.

Does intel have a working 10 series device tree for u-boot which includes pcie that I can see? I'd like to see how the pcie module is described in socfpga.dtsi. Specifically I'd like to see how the bridges are described and how the device ranges are set in the PCI module.

Using the linux socfpga.dtsi in u-boot does not work. From what I have been able to determine, u-boot does not support hierarchical device trees. But even with a flattened tree using the proper range description:

ranges = <0x82000000 0x00000000 0xc0000000 0x00100000>;

u-boot does not grok that the starting address can be different for PCI than it is for the CPU. The above line specifically states that the 32 bit, non-prefetch memory is mapped to 0x0 for PCIe devices and to 0xC0000000 for the CPU, but u-boot does not program BUS 1 BAR0 correctly and even if I hack it to do so, it fails to recognize that there is memory in CPU address space 0xC0000000 and produces this error message: (Note: I have added printfs to multiple pci and nvme driver codes to produce extra output)

pci_bus_addr = 0xc0000000
_dm_pci_bus_to_phys: hose->region_count = 2
Looking for address: 0xc0000000
loop: 0:
Section: 0, bus_start = 0x0, size = 0x100000
loop: 1:
_dm_pci_bus_to_phys: hose->region_count = 2
Looking for address: 0xc0000000
loop: 0:
Section: 0, bus_start = 0x0, size = 0x100000
loop: 1:
Section: 1, bus_start = 0x0, size = 0x40000000
pci_hose_bus_to_phys: invalid physical address

I tried to fake out u-boot by adding more "memory" at 0xc0000000, but apparently it only pays attention to main memory and the pcie ranges variable. If I add the memory to pci ranges, it does not appear to like when the memories collide, which makes perfect sense.

If intel has a working dts for u-boot to detect the pcie interface and utilize it properly, I would very much appreciate seeing that file.

In the meantime I will continue to try to appease the u-boot gods with my offerings of printf's and dtsi files.