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Vince's avatar
Vince
Icon for New Contributor rankNew Contributor
7 years ago

When using the "DDR3 SDRAM Controller with UniPHY" why does the generated .sdc specify the DDR3_ck and afi_clk at 80% of their specified rate from Qsys?

In Qsys I specify the "Memory clock frequency" as 500MHz. After compilation I run the timing analyzer, when I run "Report Clocks" it shows: DDR3_CK: 400MHz pll_afi_clk: 200MHz When I run "Report F...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

​Hi Vince,

May I know what is the speed grade of the device used? It would be better if you can share with me the full part number of the device 😊

Also, is there other clock source used beside afi_clk? The reason I ask this because using another clock would cause Qsys to automatically instantiate clock-crossing logic, potentially degrading performance.

Regards,

NAli1