VHDL Type Mismatch error indexed name returns a value whose type does not match

Which one in better XILINX or QUARTUSII Altera compilers.?

1. XILINIX

2. QUARTUS II Altera

3. Speed

4. Engine

5. License Price

6. Interface Freindly

7. Problem Help availability

8. Number of forums

9. Libraries builtin

10. Resources Consumption of PC

I see you're trying to port map a std_logic to a IO8. That's illegal.

stage9: SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(0), Q(0));

Both T(0) and Q(0) and std_logics and not IO8. But in your entity, you've declared your ports as IO8:

ENTITY SWITCHBOARD_EB007 IS PORT (

...

BIT_IN_SWITCH: IN IO8;

BIT_OUT_SWITCH: OUT IO8);

END SWITCHBOARD_EB007;

So you can't port map a std_logic to an IO8. Or, to be more explicit, you can't port map a subelement of IO8 to an IO8.

Did you try port mapping the whole IO8 bus? I'm not sure what you're trying to do here, but my guess is you should have an array for T and Q. Something like this:

SIGNAL T is array(7 downto 0) of IO8;

SIGNAL Q is array(7 downto 0) of IO8;

Then the rest of your code should work.

SWITCHBOARD_EB007 PORT MAP (CLK_IN_CPLD, RESET_CPLD, T(0), Q(0));

should work now since:

T(0) and Q(0) are both having IO8 type, and you have 8 of them for each T and Q.

I haven't tried this, but I'm _quite_ sure this is the problem. Just check it out and let us know if it works.

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creating your own array of std_logic is the main problem. why are you not using std_logic_vector?

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:):-P:cool:

Dear Tricky,

You did an awesome Trick. Your solution was bang on target. Thanks. Can you explain (its optional) when arrays are used? I think not for ports declaration but for internal wrings I mean support variables like T and Q in my code. Am I right Tricky GURU? Also please solve my timing mismatch problem. Thanks GURU.

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:):-P:cool:

Dear Tricky,

You did an awesome Trick. Your solution was bang on target. Thanks. Can you explain (its optional) when arrays are used? I think not for ports declaration but for internal wrings I mean support variables like T and Q in my code. Am I right Tricky GURU? Also please solve my timing mismatch problem. Thanks GURU.

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Arrays are used when you want to create a bus. But in VHDL as std_logic_vector is a standard type, creating your own array of std_logic is a silly idea. But feel free to make arrays of anything else (like arrays of std_logic_vector, integer, unsigned, signed etc).

The warnings are because you have no timing constraints file.

What is a timing constraints file? Can you provide one or where can I get it for my project? Is it dependent upon family device CPLD etc....?

Please let me know how can i write one if needed and integrate it in the project.?

Many thanks

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What is a timing constraints file?

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Learn about the TimeQuest Timing Analyzer. You will find more about what timing constraints are and how to set it. There's an SDC format which is a standard format used in the industry.