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Altera_Forum
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16 years ago

VHDL default signal state bug ?

We tried to do a very simple thing: a demultiplexer that enables one of several gates according to the state of an n-signal vector. (Just static, no Flipflops involved.) So we defined a 2^n sig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

This did not work (seemingly load(i) always was 0 in some or all cases ): 


signal load: std_logic_vector (63 downto 0) := (others => '0'); 
...
load(conv_integer(address)) <= '1';
...
  < now we use load(...)  >
...
This did work: 


signal load: std_logic_vector (63 downto 0);
...
G1: for i in 0 to 63 generate
begin
  load(i) <= '1' when (conv_integer(address) = i) else '0';
end generate G1
...
  < now we use load(...)  >
...
-Michael