Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Verilog Constants/Paremters accross Verilog Files?

Hi Guys,

I'm teaching myself verilog atm, (i've done small VHDL before).

My question is:

how can i define and share constants accross .v files?

For instance in C: Say you want to define a constant "SIZE" to be value "5"; and you use this definition accross many files. To do so you put it in a .h file and# include that .h where needed.

is there a verilog practice that does a similar thing?

Some brief googling i couldn't see a way, so if there isn't what is best practice for that?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The Verilog preprocessor has an `include statement for this purpose.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    It is possible to do so. As fvm (http://www.alteraforum.com/forum/member.php?u=3117) sad the `include statement could be used. To define a global constant you can use the `define statement into a separate verilog file and than include it where needed in your code. Here is an example:

    included_file.v: 

    
`ifndef INCLUDED_FILE
     `define SIZE 8'd5
`endif
    Best regards,

    VT
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    It might also be worth looking into packages. Although the `include is easy, I've found it more difficult to debug, as the file is read in "behind the scenes" and so it's hard to figure out what's going on. I think packages are more formal. (I also prefer formally passing the parameter in alongside the ports whenever possible). I think you can get by with both, and I don't do enough coding to really have a good handle, but would be curious if others had an opinion on the best way to handle this?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    It might also be worth looking into packages.

    --- Quote End ---

    This would be the standard means in VHDL designs. I'm not quite sure which Verilog element you're adressing with "packages". As far as I'm aware of, there's no suitable Verilog option besides included file constants and module parameters passed through the hierarchies.