Using PLL "lock" signal as the async reset in Verilog

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You do not want to use PLL lock as a reset signal directly. Not all PLL locked outputs have a debounce/deglitch filter, so they may toggle for a while before they stay in a static state.

Download the code associated with this PCIe test

http://www.alteraforum.com/forum/showthread.php?t=35678

There's a deglitch/debounce filter in there you can use to "clean-up" the locked signal. You can then decide whether to use the "clean" signal as a synchronous or asynchronous reset signal.

Cheers,

Dave

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Hi Dave,

First of all I hope you don't mind about my english, it's not my mother language. I'd like to know why you set the locked filter time to 0.5ms (25000 cycles in 50MHz), since Cyclone IV DS indicates Tlock = 1ms I figured out it might be set to 50000. Can you tell me more about it?

Thank's!

Anderson