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Altera_Forum's avatar
Altera_Forum
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15 years ago

TimeQuest Timing Analyzer

Hello,

I'm using TimeQuest Timing Analyzer for the first time to reduce the critical path of my design. I'd like to know the different steps to improve the maximum clock frequency. Right now, I plan to:

- Check the fitter settings to improve performance instead of area.

- Create partitions (I don't really know how it works for the moment).

- Improve adders performance and replace state machine with mux.

Does somebody have any additionnal clue ?

Thanks !

Julien

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Ok great, I don't have any hold slack anymore.

    No, I don't use clock gating. I guess clock gating is useful to minimize power consumption, isn't it ?

    The PLLs I've generated have an asynchronous reset.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If I take a look to the critical path, it is populated with a WideOR instance, that is actually implemented for huge "case" statement. Do you know another way to do "case" or "casex" statement ? Maybe I can try to use a multiplexer, I don't really know if it will be efficient.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hard to say.

    You may have just to change your design and get rid of that huge case.

    If you want to work at 100-200MHz, you can't have much combinational logic between each level of registers.