Contributor
Super ContributorThe clocks you have in the .sdc file are the base clocks, not the generated clocks from the PLL. derive_pll_clocks automatically generates clocks from your PLL settings based on those input reference clocks to the PLL. If you want those clocks coming out of your PLLs (instead of just coming in from the board), you have to set your PLL settings to multiply or divide by 1, basically mirroring the base clocks. Is that what you are trying to do?
ContributorHi sstrell,
Yes, in sdc there are two base clocks and generated clock automatically generated from PLLs by derive_pll_clocks command.
Let me explain what's going on.
This is created as an example of strange behaviour test project. It has two base clocks, and the whole sdc file is like it should be - one clock is phase shifted from another.
The clocks enter FPGA, go inside two PLLs, and PLLs just multiply clocks by 2 and output them. After that there is a simple code, consisted of two D triggers, one used for catching info from input port and clocked by first_PLL output,
and second trigger catches info from first trigger clocked by second_PLL output. The output of second trigger emerges to output port.
So, after fitter Timequest shows clock tree with a bug - generated clock from second PLL starts from wrong time in ns. It is also interesting that if I change second base clock waveform,
everything is correct for waveforms -waveform { 1.000 11.000 } -waveform { 2.000 12.000 } -waveform {3.000 13.000 } But starting from -waveform { 4.000 14.000 } I'm observing strange behaviour.
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Best regards,
Ivan
