ContributorTimeQuest can't analysis the clock from the PLL
The problem is as follows.
I need a MUX to switch the clock between normal mode and test mode. And I don't care about any transient state when clock switching.
The ending shows the design. 'pll_c4_sw' is the switched output clock. Some IP use 'pll_c4_sw' as a clock. 'pll_c4' is the clock from the PLL. 'clk_pin' is the input clock from the combinational circuit.
( I use ALTPLL to generate pll_c0~pll_c5.
Unfortunately, Quartus13.1 tell me that "PLL "pll|altpll_component|auto_generated|pll1" has parameters clk4_multiply_by and clk4_divide_by specified but port CLK[4] is not connected." when I use the Stratix III device. TimeQuest can't also analysis the timing on pll_c4 becuse TimeQuest can't find pll_c4 which is equal to clk[4] after Fitter.
Could someone please tell me what happen there? Thank you very much.
Design:
assign pll_c4_sw = sel? pll_c4 : clk_pin;
SDC command:
create_generated_clock -name pll_c4 -source [get_pins pll|altpll_component|auto_generated|pll1|inclk[0]] -multiply_by 1 -divide_by 4 [get_pins pll|altpll_component|auto_generated|pll1|clk[4]]
Hi SyafieqS_Intel, finally, I use the command, /*synthesis keep */, to keep relative port so that TimeQuest can find the CLK[4] port of the PLL.
The CLK[4] port of the PLL in post-fit is "pll|altpll_component|auto_generated|pll1|clk[4]". Thank you, SyafieqS_Intel, very much.
