Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Test benching LVDS ports

I have a Verilog design that I'm simulating with a Verilog test bench using Altera-ModelSim. The desgin has LVDS ports and when the simulation is run ModelSim complains about unconnected xxx(n) ports...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes this is a gate level sim. How do I drive the (n) pins from the Verilog test bench? Or, how do I explicitly define the (n) pins in the device Verilog file? I just left the (n) pins undefined and Quartus automatically assigned them, so there is no definition for these pins in the Verilog design file. Is there a way to explicitly define the (n) pins in the design file?