Honored ContributorHi, i have a VHDL project with some custom record type bus. All worked until today. Suddenly all logic that use custom record type is synthesized away. I don't know why. I didn't make any changes on sources and i can't find a solution.
This is very strange and not easy to resolve. I have Quartus 13.1 web edition Thanks
Honored ContributorUsually logic being synthesised away is because you left a clock stuyck at 0/1, reset held high or outputs left unconnected.
The record type itself is not the problem Why not post the problem code?Honored ContributorIf i open the RTL viewer all signal and bus are present and correctly connected but when i open Technology map viewer more than 50% of the design is not present. During analysis i receive this message:
Warning (14285): Synthesized away the following RAM node(s).Honored ContributorIt determined your RAMs were not needed for some reason - I suggest you follow their connections.
Honored ContributorI found this Info on report:
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array into its bus I have defined 4 type of record in my design package: 1 type include only std_logic_vector with the same dimension 1 type include only std_logic 2 type iclude both std_logic_vector and std_logic. Is this the problem?Honored ContributorNo - whats probably happening is part of the signals of the record type are being synthesised away, so it can no-longer maintain the record type representation in the Technology map viewer.
This is a problem with your design - not with your record types.Honored ContributorWhat appened inside an entity if i use only part of the record signals?
Honored ContributorIt will maintain the record, or use the local name.
Honored ContributorEvan after remove all the logic that use the record quartus synthesized away the rest of the logic even if this logic doesn't depend by the removed logic
