SOPC Builder Error: Can't generate 2X sampling clock signal...

Yeah, I finally got it. In SOPC Builder, double click on the CPU to bring up the options window for it. Click on the "JTAG Debug Module" tab and then down in the bottom left corner, under "Advanced Debug Settings" there's a checkbox for "Automatically generate internal 2X clock signal". After unchecking that box, the error will go away and you can generate your design. Unchecking the box doesn't seem to have any negative effect as I've now been able to generate the design, synthesize it in Quartus and deploy it on the board including using the NIOS II IDE to reprogram the processor inside and use the debugger with it. Hope this helps.