Altera_Forum
Honored Contributor
14 years agoSignalTap 11.0 enters infinite loop with negative array indexes
Just reporting a bug. It was really my fault, but it's clearly a corner-case that Altera has not considered with SignalTap.
SignalTap will enter an infinite loop if you attempt to add (in the "Setup" tab, "SignalTap: pre-synthesis" selected for signal search) a verilog array which has a negative index. Ate up my entire 8GB of system memory. :) Haha. Anyway, should be a really easy bug fix if the right person at altera reads this. Not sure if it happens in the latest version of Quartus. Here is the code that caused the bug (C_NUM_BITS was set to 0 by mistake, it should have been 1): `define C_NUM_BITS 0 output reg [`C_NUM_BITS-1:0] my_reg; The Quartus compiler generated a valid programming file but it did say: ; my_reg[-1] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; So quartus handled it just fine, but SignalTap lost it's mind and started eating my machine. Hehe.