New Contributorrecovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the top.
background: clk freq is 416Mhz; all design use asynchronous reset;
after fitting all design, the timing report about recovery violation has -1.8ns.
for one timing path, the start point is reset_sync flop2, the end point is aclr port of one flop in the module B. from the following figure 1, I find the distance start point and end point is not far apart but the routing delay is nearly 4.386ns. and How I fix the timing? Doesn't the reset route go through global network?
figure 1:
for compasion，I have taken the follwoing screenshot of the common path routing as figure 2
here, the path from start point pll to clk port of reset_sync flop spans nearly the fabric fpga, but the actual routing delay is only 4.04ns.
figure 2:
