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Scarlet
New Contributor
New ContributorStrange issues on FPGA
Hi All, I wrote a simple finite state machine Verilog code and ran it on the FPGA, but it never runs stably. My environment: - MAX10 10m08 EVB - Quartus Prime Lite 23.1.1 My Verilog Code: ...
FvM
Super Contributor
Super ContributorI agree with above post that shown timing recordings don't give much information to debug the issue, except for the simple fact that the state machine is stuck.
That's not strange but a well-known effect of state machines reading asynchronous input signals without necessary synchronizer chain. If the input changes simultaneous with clock edge, the FSM can jump to an illegal state and possibly never leave it.
That's not strange but a well-known effect of state machines reading asynchronous input signals without necessary synchronizer chain. If the input changes simultaneous with clock edge, the FSM can jump to an illegal state and possibly never leave it.
ScarletNew Contributor
New Contributor
@FvM wrote:
I agree with above post that shown timing recordings don't give much information to debug the issue, except for the simple fact that the state machine is stuck.
I've added additional explanations in the previous response.
@FvM wrote:
That's not strange but a well-known effect of state machines reading asynchronous input signals without necessary synchronizer chain. If the input changes simultaneous with clock edge, the FSM can jump to an illegal state and possibly never leave it.
Yes, I learned after working with FPGA that if the input changes simultaneously with the clock edge, it can cause errors. That's why I tried adding synchronization to wait for the external signal to stabilize, but it seems to not resolve the issue of not receiving the external data_valid signal.
data_valid_sync1 <= data_valid; data_valid_sync2 <= data_valid_sync1;
