Questa not showing signals from verilog models

Well, I remembered the alias created by Quartus Pro:

alias ld_debug "
dev_com
com
elab_debug
"

However when I enable that, questa barfs:

# Questa Intel FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# ** Error (suppressible): (vlog-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases.
# Errors: 1, Warnings: 0

So questa has disabled this option: -voptargs=+acc

I can suppress it, I just have to figure out how.

It seems to me that the Quartus qsys tool needs to be updated to add an option for enabling access to modules on a module by module basis when it creates msim_setup.tcl.

If anyone knows a better way to do this, I'm all ears.