Implementing MIPI DSI-2 on an Agilex 5 device

First

I tested the following configuration for 800x96 only, and it passed the simulation successfully.
It is configured as close as possible for simulation purposes. 
Due to a limitation I discovered — the frame height in the simulation is fixed at 96 — it effectively simulates a resolution of 800x96.
The only change you’ll need to make for your final hardware system is to change `C_TIM_VTOTAL` to `630` to update the active height to `600`. 
(Note: this change will not pass simulation due to the limitation in the simulation components.)

You may follow the `.ip` settings below to try it out.
For the simulation variant, you can select either *fast sim* or *full sim*, depending on your needs.

Second

Regarding the black-box IP component:

You can have the IP itself, but when you generate the IP, Platform Designer will automatically create a black-box Verilog file.
For example, you can:

1. Select the **DSI-2 IP** from the IP Catalog in Quartus.  
2. Name the new IP `dsi_example.ip`.  
3. Configure the IP as required.  
4. Generate the IP (not the example design).  
5. Look in the new `dsi_example` folder under the Quartus project folder and find `dsi_example_bb.v`, which is an empty Verilog component with the correct I/O for the selected configuration.

Regards,  
Wincent