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Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

Questasim UVM macros

Hi ,

I am trying to compile and run simulation in Questasim , using uvm libraries and uvm packages.

But i am getting error that include files not defined , although these uvm files are installed in verilog_src folder at Questasim installed path.

See screen shots and sv files attached.

Any tip or guide how to direct compiler to pick the installed uvm files.

Thanks,

Regards,

# three files are :

package file :

////////////////////////
`include "uvm_macros.svh"
`include "uvm_pkg.sv"
package uvm_sim_pk;

import uvm_pkg::*;

class my_transaction extends uvm_sequence_item;

`uvm_object_utils(my_transaction)

rand int addr;
rand int data;
rand bit r0w1;

function new (string name = "");
// Without a string name the transaction would be anonymous
super.new(name);
endfunction: new

constraint c_addr { addr >= 0; addr < 256; }
constraint c_data { data >= 0; data < 256; }

endclass: my_transaction

Simulation

21 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    7 months ago

    Which specific simulator tool are you using?

    Correct me if I am wrong. The tool you are using seems like it is from Siemen Questasim and not the Questa Intel FPGA Edition.

    The UVM library is pre-compiled with Questa Intel FPGA Edition.

    You may try to consult this at the Siemen forum or you can try download and use our Questa Intel FPGA Edition simulator tool.

    Regards,

    Richard Tan

    Tool Info:
    Questa Intel FPGA Edition-64 2024.1

    Revision: 2024.04

    • Fpga_Egr_2025's avatar
      Fpga_Egr_2025
      Icon for Occasional Contributor rankOccasional Contributor
      7 months ago

      HI tried to compile and run using Intel Questasim , but still it wont find uvm macros :

      And i can also see that the uvm package files in the linked libraries :

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    7 months ago

    Try using below command with +incdir:

    vlog -sv -work work +incdir+$UVM_HOME/src uvm_sim_pk.sv

    Make sure $UVM_HOME points to your UVM installation directory.

    example:

    vlog -sv -work work +incdir+C:/<installation directory>/questa_fe/verilog_src/uvm-1.1d/src uvm_sim_pk.sv

    Then vsim example:

    vsim -c -sv_lib <installation directory>/uvm-1.1d/win64/uvm_dpi work.my_tb -do "run -all; quit"

    You may checkout this webpage for further details:

    https://blogs.sw.siemens.com/verificationhorizons/2011/03/08/using-the-uvm-10-release-with-questa/

    Do note that the Questa Intel FPGA edition does not support advanced verification features such as randomization. You might see below error message:

    # Error: Failure to checkout svverification license feature.

    # Fatal: (vsim-7099) Unable to check out a verification license for the randomize() feature.

    In that case, you might need to use back the Siemens Questa version. (not Intel/Altera version)

    Regards,

    Richard Tan

    • Fpga_Egr_2025's avatar
      Fpga_Egr_2025
      Icon for Occasional Contributor rankOccasional Contributor
      7 months ago

      Hi I tried to compile and include in the working directory , but no success in linking "uvm_macros.svh" .

      It is dependent on "uvm_tlm_imps.svh" , which vlog did not complain about , but when i tried to include "uvm_macros.svh" it refers to "uvm_tlm_imps.svh".

      Any clue what should be the compile order ? to fix this

      See image attached.

      Thanks

      Regards,

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    7 months ago

    Are you using correct command?


    I think you should run

    vlog -sv -work work +incdir+C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src uvm_sim_pk.sv

    (there is a space in between uvm_sim_pk.sv and _incdir+C...)


    instead of

    vlog -sv -work work +incdir+C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src/tlml/uvm_tlm_imps.svh


    Regards,

    Richard Tan


  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    7 months ago

    Again, you use the wrong command.

    Use:

    vlog -sv -work work +incdir+C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src uvm_sim_pk.sv

    Not

    vlog -sv -work work +incdir+C:\intelFPGA_lite\24.1std\questa_fse\verilog_src\uvm-1.1d\src uvm_sim_pk.sv

    That's likely what mess up the path name.

    Regards,

    Richard Tan

    • Fpga_Egr_2025's avatar
      Fpga_Egr_2025
      Icon for Occasional Contributor rankOccasional Contributor
      7 months ago

      still its not working , i am getting error msg that questasim cannot open uvm_macros.svh in read mode.

      Although i am running questasim in admin mode .

      • RichardT_altera's avatar
        RichardT_altera
        Icon for Super Contributor rankSuper Contributor
        7 months ago

        I attached an example that I used.

        Add these script into a .do file then run the .do file. 

        vlib work
        vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src my_transaction.sv
    • Fpga_Egr_2025's avatar
      Fpga_Egr_2025
      Icon for Occasional Contributor rankOccasional Contributor
      7 months ago

      i have also tried giving specific path in the .svh file like this :


      ////////////////////////
      `include "C:/intelFPGA_lite/24.1std\questa_fse/verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh"
      `include "C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src/uvm_macros.svh"

      `include "uvm_pkg.sv"
      package sim_pk;

      import questa_uvm_pkg::*;
      import uvm_pkg::*;

      But get this error :

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    7 months ago

    Is the file named uvm_sim_pk.sv (and not uvm_sim_pkg.sv)?


    Make sure the package is called uvm_sim_pkg inside the file — the spelling must be exact.


    Regards,

    Richard Tan


    • Fpga_Egr_2025's avatar
      Fpga_Egr_2025
      Icon for Occasional Contributor rankOccasional Contributor
      7 months ago

      yes in one module "dut" it was spelled wrong but still compilation results in error of not finding the uvm_pkg .

      i have made some changes see below :

      //uvm_sim_pk//

      ////////////////////////
      `ifndef UVM_SIM_PK
      `define UVM_SIM_PK

      package uvm_sim_pk;
      `include "C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh"
      `include "C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src/uvm_pkg.sv"
      `include "uvm_macros.svh"
      import uvm_pkg::*;

      class my_transaction extends uvm_sequence_item;

      `uvm_object_utils(my_transaction)

      rand int addr;
      rand int data;
      rand bit r0w1;

      function new (string name = "");
      // Without a string name the transaction would be anonymous
      super.new(name);
      endfunction: new

      ///////////////////////////////////////////////////////////////////////////////////////////////

      //top.sv//

      `include "uvm_sim_pk.sv"
      module top;

      import uvm_sim_pk::*;

      dut_if dut_if1 ();

      dut dut1 ( .i_f(dut_if1) );

      // Test classes are better placed in a package, but defining the class here
      // avoids the need to introduce set_config_db to connect the virtual interface
      // in this very simple example

      //////////////////////////////////////////////////////////////////////////////////////////////

      //dut.sv//


      interface dut_if();
      `include "uvm_pkg.sv"
      `include "uvm_macros.svh"
      import uvm_pkg::*;

      int addr;
      int data;
      bit r0w1;

      modport test (output addr, data, r0w1);
      modport dut (input addr, data, r0w1);

      ////////////////////////////////////////////////////////////////////////

      // do file //

      ## Questasim do file ##
      vlib work
      vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src uvm_tlm_imps.svh
      vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src uvm_pkg.sv
      vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src uvm_sim_pk.sv
      vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src dut.sv
      vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src top.sv

      /////////////////////////////////////////////////////////////////////////

      But i still this error :

      • RichardT_altera's avatar
        RichardT_altera
        Icon for Super Contributor rankSuper Contributor
        7 months ago

        Its a UVM guideline to use .sv extensions for compile files and .svh for `include files.
        You're trying to compile uvm_tlm_imps.svh directly:

        vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src uvm_tlm_imps.svh

        This is incorrect. Remove that line — the uvm_tlm_imps.svh file will be included inside other UVM source files (like uvm_pkg.sv) automatically.

        Regards,
        Richard Tan

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    7 months ago

    We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.


    If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    The community users will be able to help you on your follow-up questions.


    Thank you for reaching out to us!


    Best Regards,

    Richard Tan