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ldm_as's avatar
ldm_as
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

[Questa] Compilation libraries for Verilog/SystemVerilog

Hi All, I know that it's possible to compile VHDL files to different libraries. Is it possible to do the same with Verilog? Is it possible the different compilation libraries will have the same ...
MEIYAN_L_Intel's avatar
MEIYAN_L_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

May I know what is different libraries here and which libraries do you mean?

Based on my understanding, there is no library in verilog but you can use Verilog header file that can allow you to do some component functionality.

You can write a verilog file and then include it in another verilog file. In this verilog file, you might instantiate the component used. You may try the code as stated in link below:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07231998_9862.html

Thanks

ldm_as's avatar
ldm_as
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Cannot I use the 'vlog -work <libname> <filename>' command in order to compile the <filename> file into <libname> library?

The situation is so that I have a design with two modules, which have the the same name but a different functionality and they are located in the different hierarchies of the design...

So, I'm seeking a way how to compile the design without touching the files... So I thought that compiling the design into the different libraries could give a solution...