Altera_ForumHonored Contributor13 years agoPreserving WYSIWYG LUT input assignments I am working on a Stratix III design in which I need to very precisely control delay paths on some outputs from my design. In a previous version of my design, I hand instantiated WYSIWYG cells and u...Show More
Altera_ForumHonored Contributor13 years agoThanks for some insights to the amazing world of routing constraint files!
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