Modelsim design size limit buggy and or misleading in Quartus Lite 19.1

Hi, I am trying to simulate a small design totaling just 1025 lines of VHDL including the Megawizard parts & test bench YET Modelsim prints a warning

# ** Warning: Design size of 17912 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.

# Expect performance to be adversely affected.

And goes into totally slugged mode making itself unusable.

Why is there such a large discrepancy between the actual size of the design and that claimed by modelsim ? Is this a bug ?

The Megawizard parts are a PLL and two small block rams, the rest of the code consists of a top module joining two lower level modules, then of course there is a small test bench.

Has anybody else experienced this problem ?