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Altera_Forum
Honored Contributor
Honored ContributorMemory coding style
Dear all,
I've coded two versions of a single-port synchronous RAM with variable read/write width. However, first design results in 1307 ALMs utilization, while second results in 757 ALMs utilization, both compiled with Quartus Prime 16.0.0 Build 211 Lite Edition. Any idea why?typedef enum logic {CHAR, UCHAR, SHORT, USHORT, INT} DataType;
module Memory(input DataType dataType, input storeData, input address, input clock, store, write, output logic excep, output loadData);
logic memory ;
always_ff @(posedge clock)
case (dataType)
CHAR:
if (store) memory]]] <= storeData;
else loadData <= {{24{memory]]]}}, memory]]]};
UCHAR:
if (store) memory]]] <= storeData;
else loadData <= {24'h0, memory]]]};
SHORT:
if (address != 1'h0) excep <= 1'h1;
else if (store) memory]] <= storeData;
else loadData <= {{16{memory]]}}, memory]]};
USHORT:
if (address != 1'h0) excep <= 1'h1;
else if (store) memory]] <= storeData;
else loadData <= {16'h0, memory]]};
INT:
if (address != 2'h0) excep <= 1'h1;
else if (store) memory] <= storeData;
else loadData <= memory];
endcase
endmoduletypedef enum logic {CHAR, UCHAR, SHORT, USHORT, INT} DataType;
module Memory(input DataType dataType, input storeData, input address, input clock, store, write, output logic excep, output loadData);
logic memory ;
always_ff @(posedge clock)
case (dataType)
CHAR:
if (store)
case (address)
1'h0: memory] <= storeData;
2'h1: memory] <= storeData;
2'h2: memory] <= storeData;
2'h3: memory] <= storeData;
endcase
else
case (address)
1'h0: loadData <= {{24{memory]}}, memory]};
1'h1: loadData <= {{24{memory]}}, memory]};
1'h2: loadData <= {{24{memory]}}, memory]};
1'h3: loadData <= {{24{memory]}}, memory]};
endcase
UCHAR:
if (store)
case (address)
1'h0: memory] <= storeData;
2'h1: memory] <= storeData;
2'h2: memory] <= storeData;
2'h3: memory] <= storeData;
endcase
else
case (address)
1'h0: loadData <= {24'h0, memory]};
1'h1: loadData <= {24'h0, memory]};
1'h2: loadData <= {24'h0, memory]};
1'h3: loadData <= {24'h0, memory]};
endcase
SHORT:
if (address != 1'h0) excep <= 1'h1;
else if (store)
case (address)
1'h0: memory] <= storeData;
2'h1: memory] <= storeData;
endcase
else
case (address)
1'h0: loadData <= {{16{memory]}}, memory]};
1'h1: loadData <= {{16{memory]}}, memory]};
endcase
USHORT:
if (address != 1'h0) excep <= 1'h1;
else if (store)
case (address)
1'h0: memory] <= storeData;
2'h1: memory] <= storeData;
endcase
else
case (address)
1'h0: loadData <= {16'h0, memory]};
1'h1: loadData <= {16'h0, memory]};
endcase
INT:
if (address != 2'h0) excep <= 1'h1;
else if (store) memory] <= storeData;
else loadData <= memory];
endcase
endmodule5 Replies
Altera_ForumDid you follow the coding guidelines for rams?
- Altera_Forum
For the one that has the highest ALMs utilization, yes! ^^
- Altera_Forum
Were you deliberatly trying to target ALMs rather than the internal ram blocks? If you were, then have you verified that the code for both is functionally equivolent?
- Altera_Forum
Not deliberately targeting ALMs. I just realized second design results in fewer resources utilization.
Both codes are equivalent, look at it! - Altera_Forum
I would build a tasty bench to prove they are equivalent.
