Is anybody else completely dissatisfied with this new forum?

You're right, that should not happen. Thanks for noting it. I'll take it back to our team to address.

Also, the FPGA team is still working on creating those sub categories everyone's been asking about. They're in process now and we expect them to go live in January for you.

Thanks for everyone feedback and input, we appreciate it.

Mary T.

Community Manager

Well I can't sleep and have exausted my other go-to's and decided to give it another try. My biggest issues, apart from the previously mentioned is the total lack of mobile browser compatibility. All I see on my 10" tablet is a big blue bar wit an intel logo and some links, another big blue bar with community and my account number (that now I seem to be able to edit but there is no save button) and below that a search bar. Ah, if I scroll the searchbar disappears and I can now see the lines :). It would be really great to see thhe texts full-width, or at least twice the current size. Apart from my keyboard my screen is showing mabe 10% interesting stuff. i.e. this textbox.

Also I dislike the js void links on the first page. If I just browse the forum to see if I can help someone out I would like to visit that page and then open the 8 links in separate tabs (or have a recent posts page with all of them) instead of going back to the first page. Each time and clicking trough the links. But I seem to remember chatting about this stuff with a research group, did none of that feedback make it trough?

When me and my collegues were complaining about Xilinx' documentation and forum I used to suggest using Intel/Altera partially because of the good forum support, searching wasn't always easy, but it was easier to use than this. I've stopped suggesting Intel now. I propose Lattice instead.

[Edit] Now I know why the void links are there, more than 4 tabs crashes the browser. Positive thing: this edit box is exactly what I wanted when I said the stuff about screen utilization. But where is the save button here? Found it, I just needed to rotate into portrait orientation...[/edit]

Another problem is that the threads no longer show as closed. I can see a Best Answer but that itself shouldnt mean no further replies should be posted. Previously, the thread showed Locked at the bottom. Not seeing that, I posted three times today only to have the posted rejected because its only then that you find out its locked.

Great point mentioned by the above user (whose name seems to be garbled for some reason). Indeed this is another regression after the update that now, all the "links" on the sections show up as "javascrip:void(0);", making it impossible to open multiple threads in parallel in different tabs. I had encountered this issue also before the update, but that was only when I did not wait long enough for the page to load completely.

Another thing to mention is that the forum really needs a proper “quote” feature; or maybe there is one but I cannot find it. The new tree-based replying could be considered as replacement for quoting, but it has a big disadvantage which is the fact that it breaks the order of the posts; i.e. if someone makes post A and someone else makes post B after it and then someone else replies to post A directly, the reply will end up before post B even though it was made later. In a big active thread, this is going to make it very difficult to tell which post is new and which is old.

like I wrote before I missed recent post, but I found something like it: on https://forums.intel.com/s/ and then click the all discussions, but it would be nice to have this for FPGAs only and not for ALL Intel products.

As to my garbled nickname I cannot change it to anything that resembles the nickname I had on the Alteraforum (pietervanderstar).

It would also be nice to have support for Verilog and VHDL in the code markup. Now only a few of the keywords are recognised, while sometimes the Verilog ' operator (or whatever the proper name is) sometimes gets mistaken for start of string/comment as all text after is green.

Just got a new issue, the view more button disappeared, which means I cannot view the last post in longer threads (such as this one).

Hi @Pvand1​ ,

Regarding: the view more button disappearing on you, can you let me know which browser you're using?

In the meantime, from inside the very first post, you can select 'Go To Latest Reply". Does that help?

Let us know on that browser so we can investigate for you. Thank you,

Mary T.

Community Manager

I would like to add my agreement with all of the above posts.

This design is a major step backward. Intel, it is your intent to drive users from this forum? If so, this design will do it!!!!

This forum design = Windows 8. And we all know how that turned out!

@HazlinaR_Intel​ ,

Well, here is goes with random code off the internet:

----------------------------------------------------------------------
-- GCD CALCULATOR (ESD book figure 2.11)			
-- Weijun Zhang, 04/2001
--
-- we can put all the components in one document(gcd2.vhd)
-- or put them in separate files 
-- this is the example of RT level modeling (FSM + DataPath)
-- the code is synthesized by Synopsys design compiler
----------------------------------------------------------------------
 
-- Component: MULTIPLEXOR --------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity mux is 
    port(	rst, sLine: in std_logic;
		load, result: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 3 downto 0 )
    );
end mux;
 
architecture mux_arc of mux is
begin
    process( rst, sLine, load, result )
    begin
	if( rst = '1' ) then 
	    output <= "0000";		-- do nothing
	elsif sLine = '0' then 
	    output <= load;		-- load inputs
	else 
	    output <= result;		-- load results
	end if;
    end process;
end mux_arc;
	
-- Component: COMPARATOR ---------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity comparator is
    port(	rst: in std_logic;
		x, y: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 1 downto 0 )
    );
end comparator;
 
architecture comparator_arc of comparator is
begin
    process( x, y, rst )
    begin
	if( rst = '1' ) then 
	    output <= "00";		-- do nothing
	elsif( x > y ) then 
	    output <= "10";		-- if x greater
	elsif( x < y ) then 
	    output <= "01";		-- if y greater
	else 
	    output <= "11";  	        -- if equivalance. 	
	end if;
    end process;
end comparator_arc;
 
-- Component: SUBTRACTOR ----------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity subtractor is
    port(	rst: in std_logic;
		cmd: in std_logic_vector( 1 downto 0 );
		x, y: in std_logic_vector( 3 downto 0 );
		xout, yout: out std_logic_vector( 3 downto 0 )
    );
end subtractor;
 
architecture subtractor_arc of subtractor is
begin
    process( rst, cmd, x, y )
    begin
	if( rst = '1' or cmd = "00" ) then 	-- not active.
	    xout <= "0000";	
	    yout <= "0000";
	elsif( cmd = "10" ) then 		-- x is greater
	    xout <= ( x - y );
	    yout <= y;
	elsif( cmd = "01" ) then 		-- y is greater
	    xout <= x;	
	    yout <= ( y - x );
	else 
	    xout <= x;  			-- x and y are equal
	    yout <= y; 		
	end if;
    end process;
end subtractor_arc;
 
-- Component: REGISTER ---------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity regis is
    port(	rst, clk, load: in std_logic;
	        input: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 3 downto 0 )
    );
end regis;
 
architecture regis_arc of regis is
begin
    process( rst, clk, load, input )
    begin
	if( rst = '1' ) then 
	    output <= "0000";
	elsif( clk'event and clk = '1') then
	    if( load = '1' ) then	
	        output <= input;
	    end if;
        end if;
    end process;
end regis_arc;
 
-- component: FSM controller --------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity fsm is
    port(	rst, clk, proceed: in std_logic;
		comparison: in std_logic_vector( 1 downto 0 );
		enable, xsel, ysel, xld, yld: out std_logic
    );
end fsm;
 
architecture fsm_arc of fsm is
 
    type states is ( init, s0, s1, s2, s3, s4, s5 );
    signal nState, cState: states;
 
begin
    process( rst, clk )
    begin
	if( rst = '1' ) then 
	    cState <= init;
	elsif( clk'event and clk = '1' ) then 
	    cState <= nState;
	end if;
    end process;
 
    process( proceed, comparison, cState )
    begin
	case cState is 
		
	when init =>	if( proceed = '0' ) then 
			    nState <= init;
			else 
			    nState <= s0;
			end if;
			
	when s0 =>	enable <= '0';
			xsel <= '0';
			ysel <= '0';
			xld <= '0';
			yld <= '0';
			nState <= s1;
	
	when s1 =>	enable <= '0';
			xsel <= '0';
			ysel <= '0';
			xld <= '1';
			yld <= '1';
			nState <= s2;
		
	when s2 =>	xld <= '0';
			yld <= '0';
			if( comparison = "10" ) then 
			    nState <= s3;
			elsif( comparison = "01" ) then 
			    nState <= s4; 	
			elsif( comparison = "11" ) then 
			    nState <= s5;   	
			end if;
		
	when s3 =>	enable <= '0';
			xsel <= '1';
			ysel <= '0';
			xld <= '1';
			yld <= '0';
			nState <= s2;
	
	when s4 =>	enable <= '0';
			xsel <= '0';
			ysel <= '1';
			xld <= '0';
			yld <= '1';
			nState <= s2;
 
	when s5 =>	enable <= '1';
			xsel <= '1';
			ysel <= '1';
			xld <= '1';
			yld <= '1';
			nState <= s0;
			
	when others =>	nState <= s0;
			
        end case;
	
    end process;
	
end fsm_arc;
 
----------------------------------------------------------------------
-- GCD Calculator: top level design using structural modeling
-- FSM + Datapath (mux, registers, subtracter and comparator)
----------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.all;
 
entity gcd is
    port(	rst, clk, go_i: in std_logic;
		x_i, y_i: in std_logic_vector( 3 downto 0 );
		d_o: out std_logic_vector( 3 downto 0 )
    );
end gcd;
 
architecture gcd_arc of gcd is
 
component fsm is
    port(	rst, clk, proceed: in std_logic;
		comparison: in std_logic_vector( 1 downto 0 );
		enable, xsel, ysel, xld, yld: out std_logic
    );
end component;
 
component mux is 
    port(	rst, sLine: in std_logic;
		load, result: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 3 downto 0 )
    );
end component;
 
component comparator is
    port(	rst: in std_logic;
		x, y: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 1 downto 0 )
    );
end component;
 
component subtractor is
    port( 	rst: in std_logic; 
		cmd: in std_logic_vector( 1 downto 0 );
		x, y: in std_logic_vector( 3 downto 0 );
		xout, yout: out std_logic_vector( 3 downto 0 )
    );
end component;
 
component regis is
    port(	rst, clk, load: in std_logic;
		input: in std_logic_vector( 3 downto 0 );
		output: out std_logic_vector( 3 downto 0 )
    );
end component;
 
signal xld, yld, xsel, ysel, enable: std_logic;
signal comparison: std_logic_vector( 1 downto 0 );
signal result: std_logic_vector( 3 downto 0 );					
 
signal xsub, ysub, xmux, ymux, xreg, yreg: std_logic_vector( 3 downto 0 );
 
begin
 
    -- doing structure modeling here
 
    -- FSM controller
    TOFSM: fsm port map(    rst, clk, go_i, comparison, 
			    enable, xsel, ysel, xld, yld );   				 
    -- Datapath
    X_MUX: mux port map( rst, xsel, x_i, xsub, xmux );
    Y_MUX: mux port map( rst, ysel, y_i, ysub, ymux );
    X_REG: regis port map( rst, clk, xld, xmux, xreg ); 
    Y_REG: regis port map( rst, clk, yld, ymux, yreg ); 
    U_COMP: comparator port map( rst, xreg, yreg, comparison );
    X_SUB: subtractor port map( rst, comparison, xreg, yreg, xsub, ysub );
    OUT_REG: regis port map( rst, clk, enable, xsub, result );
	
    d_o <= result; 
 
end gcd_arc;
 
---------------------------------------------------------------------------