instaciating the same architecture twice gives different results

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Hello everybody!

I'm trying(!) to implement 2 OFDM transmitters in an Stratix III FPGA. I have one VHDL design for the transmitter. When I instanciate the design twice in the FPGA one of them works, but the other not.

I know this sounds like there is a flaw in the design, but I checked and double checked everything. All the signals are registered... Also TimeQuest doesn't report any errors.

After compilation of the design I checked the resource section in the fitter report, and found out that the number of resources used is slightly different. Although it doesn't supprise me this might be a problem. So I tryed to prevent Quartus from optimizing the netlist, duplicate logic etc. and create LogicLock regions for the two transmitter. But this caused Quartus 9.1 SP1 to stop with an internal error in the fitter :mad:.

Does anybody have any suggestions how to instanciate the design twice so that the results will be the same?

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Hi,

can you post the level where you instanciate the transmiiter. Only to be sure ....

Do you fully constraint your design ? Clocks, I/O, ....

Kind regards

GPK

Hi GPK,

thanks for your fast response! I attached the entity where I instanciate the IFFT, cyclic prefix etc. the top level entity of the design, and also the SDC File for the timing constraints.

kind regards

Christoph

https://www.alteraforum.com/forum/attachment.php?attachmentid=2797

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Hi GPK,

thanks for your fast response! I attached the entity where I instanciate the IFFT, cyclic prefix etc. the top level entity of the design, and also the SDC File for the timing constraints.

kind regards

Christoph

https://www.alteraforum.com/forum/attachment.php?attachmentid=2797

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Hi,

nothing strange found so far. Can you describe the misbehaviour a little bit more ?

Kind regards

GPK

ok, let me try...

I test my transmitters by activating only one subcarrier so I expect to see a single sinusodial wave on the DAC outputs, but one of the outputs (it's not always the same) oscillates in a more less random looking way.

The setup and hold times at the DAC are not violated because I use a seperate clock for every channel of the DAC (delays are different on the board), and I can adjust the clock phase during runtime so that the data are sampled correctly.

It appears to be that there is some sort of metastability problem?

There are several different clock domains in the design, but I think I handle the transistions from one clock domain to another correctly (use synchronizers, reset sequencer), and TimeQuest doesn't report any errors which it should if there is a timing violation (if my timing constraints are correct)

thanks for your help, because I'm really desperate.

Christoph

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ok, let me try...

I test my transmitters by activating only one subcarrier so I expect to see a single sinusodial wave on the DAC outputs, but one of the outputs (it's not always the same) oscillates in a more less random looking way.

The setup and hold times at the DAC are not violated because I use a seperate clock for every channel of the DAC (delays are different on the board), and I can adjust the clock phase during runtime so that the data are sampled correctly.

It appears to be that there is some sort of metastability problem?

There are several different clock domains in the design, but I think I handle the transistions from one clock domain to another correctly (use synchronizers, reset sequencer), and TimeQuest doesn't report any errors which it should if there is a timing violation (if my timing constraints are correct)

thanks for your help, because I'm really desperate.

Christoph

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Hi,

is it random which of the outputs is working ? Is it changing after a new P&R or after reset of the design ....?

Kind regards

GPK

Hi,

unfortunately I don't see a clear pattern, but I can tell that

* resetting the design doesn't make a difference

* when switching off and programming the FPGA again (same design) it sometimes works

* compiling the design again SEEMS to effect which Tx works

I know this is a very vague description, but this problem is really weird.

At the moment I'm trying to create a floorplan for the design (LogicLock regions etc.) so that the components for one Tx are in one place. But for a well implemented design it shouldn't matter where the components are located, right?

kind regards

Christoph

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Hi,

unfortunately I don't see a clear pattern, but I can tell that

* resetting the design doesn't make a difference

* when switching off and programming the FPGA again (same design) it sometimes works

* compiling the design again SEEMS to effect which Tx works

I know this is a very vague description, but this problem is really weird.

At the moment I'm trying to create a floorplan for the design (LogicLock regions etc.) so that the components for one Tx are in one place. But for a well implemented design it shouldn't matter where the components are located, right?

kind regards

Christoph

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Hi,

in TimeQuest you can get the info about "Unconstraint Paths". Maybe it good to have a look at it. Is there any kind of SW control involed ???

Kind regards

GPK

Hi,

I have to (successfully) run compilation before I can start TimeQuest, but I will take a look at the unconstrained paths...

SW control? There is a NIOS II in the design that configures the transmitters (FFT points etc.) at runtime.

thanks again

Christoph

I faced similar problem in that a proven company legacy design didn't work consistently in my hands.

It turned out to be due to flaky reset plan. The best way was to apply a different reset sequencer.

Apart from timing, make sure you power up corectly(check don't care setting). Use signaltap to check outputs as well.

thanks kaz for the suggestions.

I already use a reset sequenzer that resets the design asynchronously and releases the reset synchronously. The resets of the different clock domains are released such that the next component starts to work after the previous has been reset.

where can I find this "don't care setting"? Does it affect only registers?

I've been using SignalTap to debug the design, but I recently removed it as it will alter the timing behavior and make fitting the design more difficult.

kind regards