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Austin_7's avatar
Austin_7
Icon for New Contributor rankNew Contributor
5 years ago

I want to solve 'top level design entity is undefined' problem. Please help me.

I'm the student and the beginner at FPGA. I found some people who had the same problem. I think I checked what they did, but the problem still exists. Please help me. I uploaded one minute video. Sorry for bad English because I'm Korean student. But you can see the window and it may help you to find the problem. I also uploaded the file.

I really hope you to help me.

Thank you.

4 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor

    The module in your HDL is named "hello" which doesn't match what you've specified as the top-level entity ("2_2_Hello_Word"). Either change the HDL code or the name of the top-level entity in the project settings.

    Also note that none of that HDL code in 2_2_Hello_Word.v is synthesizable so compiling it in Quartus isn't going to do anything. The code you've written is more like what would be a simulation testbench for a simulation tool like ModelSim.

    • Austin_7's avatar
      Austin_7
      Icon for New Contributor rankNew Contributor

      I really appreciate your help. After I changed my module name, the different error which you said occurred.

      "Error (12061): Can't synthesize current design -- Top partition does not contain any logic"

      The code was from the first part of the book and I think I really have to change the book to study,,,

      Thank you.

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