How to remove the glitch like this?

Besides other signals, you are creating CK as a gated clock from clk_200 ns. Without discussing the general timing problems brought up by gated or generated clocks, I see two options to do it in a proper synchronous way:

- have a higher system clock, at least 100 ns period. This won't be a problem unless the 5 MHz clock is your primary input clock

- refer to the gated clock design suggested in the Quartus software handbook. It uses a register clocked at the negative edge to delay the gate signal.