New ContributorWhy does my Altera FIR IP, configured for interpolation by 80, produce the expected outputs when I provide 3 input samples, but fail to produce the expected behavior when I provide 10 input samples? In this case, the FIR IP keeps tready asserted high, but only generates 4 valid outputs. What could be causing this behavior? I am simulating this in Quartus Prime Lite Edition.
Occasional ContributorHello - please see attached. In reviewing the documentation, a single-channel interpolation use case is not well documented, and we are discussing internally on how to better articulate this and use the tvalid/tready on the sink side. Currently, the documentation states that it is a pass-thru from the tready on the source side (which is how it is behaving).
If you change your input to align with attached image, it should behave better. This would mean modulating the tvalid input to assert 1-in-80 clock cycles. If you receive in bursts, you should FIFO to holdoff.
New ContributorHi Jeffc,
I had tried this one, this was giving expected number of outputs.
Regular ContributorNew ContributorI am using a Cyclone V device with Quartus Prime Lite 25.1 Edition.
Here I have attached the relevant top module and testbench code.
Any guidance would be greatly appreciated.
Regular ContributorHi,
As I tried to replicate your simulation, I noticed that I would need a few other settings of your FIR II IP ie Coefficient Settings, Coefficients, Input/Output Options, Implementation Options and Reconfigurability. You may share with me the IP megawizard files. Thank you.
Regular ContributorHi,
Thanks for sharing the files. Please allow me some time to look into it and perform replication on my side. Please ping me if you do not hear back from me by early next week. Thank you.
New ContributorI am using Quartus prime lite 25.1 version.
But I was not able to see tready go low. I even tried providing inputs to the FIR once every 80 clock cycles.
Regular Contributorsaasha Would you mind to help to create a simple testbench design in QuestaSim that reproduces the issue you’re observing? Having a minimal simulation case would greatly help with replication and debugging on our side.
It would also be helpful if you could share the step-by-step procedure to run the simulation. Additionally, please let us know the specific device you are using.
Thank you for your support.
Occasional ContributorJust a thought - if you specify 6.25M input sample rate and a clock rate of 500M, you are specifying an oversample rate of 80x. This implies that you should see an input sample 1 in every 80 clock cycles on the input (and then receive full rate data @ 500M on the output). You are likely overflowing the FSM inside the IP. With that said, I believe you should be seeing tready go low. What version of Quartus / IP are you using here?
New ContributorThis is how I configured my fir ip
I have attched simulation outputs for 10 & 3 inputs.
