Does Quartus II support use of fixed point arithmatic packages in VHDL?

Yes, it is still true, and the packages are finally included with Q15.1 prime pro. If you dont have a pro licence, you'll have to provide the '93 compatible versions from off the web.

The advantage is it makes fixed point much clearer in your code:

signal f : sfixed(1 downto -14);

You shouldnt be using std_logic_vector at all to represent integers. You should only be using it to connect to IP blocks that require it, otherwise you should be using numeric_std with signed/unsigned or the fixed_pkg ufixed/sfixed. VHDL does not define any arithmatic for std_logic_vectors.