Clock network delay + internal cell delay > Minimum timing requirement

Hi Brad,

Thanks for your suggestion, I've checked the output pin delay in the resource property editor and it was already on the lowest (105ps).

Unfortunately I'm already using all available PLLs.

Is this an inherent limitation of the Cyclone II device? I would have thought 133MHz would have been reasonable, but perhaps i'll have to consider running the memory at 100MHz.

Anyone else had experience with a SDRAM controller running at this speed on a Cyclone II or similar devices?

Thanks, Evan.