I have a clock mux along the lines in "ug-qps-03-design-recommendations.pdf"I have set the output clock to be a Global Clock in the Assignment Editor and I give it's minimum period in the sdc file. I don't get any warnings of this signal in the fitter report. It is sent to an output pin as well as used internally.However the clock is not mentioned in the Report Setup Summary whereas the other clocks of interest are.I've tried a couple of variations of changing name and assigning the output clock to the internal name.Any ideas where I might be going wrong?

Hi,If create the clock in the timing analyzer, and use the auto-generated .sdc. Will it reflected?Thanks,Regards,Sheng

Many thanks for your reply.I haven't made any changes to the Assignment Editor, but deleted/renamed the old sdc file and created a new one from Timing Analyzer.These are now the active lines in the sdc file:**************************************************************create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]create_clock -name {HDMI_TX_CLK} -period 6.750 -waveform { 0.000 3.375 } [get_ports {HDMI_TX_CLK}]set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a*}]set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a*}]set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_hd9:dffpipe19|dffe20a*}]set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_gd9:dffpipe13|dffe14a*}]set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_rd9:dffpipe8|dffe9a*}]set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_qd9:dffpipe5|dffe6a*}]set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_pd9:dffpipe8|dffe9a*}]set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_od9:dffpipe5|dffe6a*}]**************************************************************After compiling the design which fitted fine and very quickly, I reopened Timing Analyzer, "Read the SDC File", double clicked "Report Setup Summary" and got a single line:altera_reserved_tck 7.788 0.000I am using SignalTap where the clock is also the missing clock HDMI_TX_CLK. SignalTap works as expected. The fitter report says it found "2 clocks" consistent with the SDC file. There are some expected warnings from not specifying the periods of input clocks that are specified in PLLs.One thing that bothers me is this line and is mentioned 5 times in the processing messages: Info (13166): Register RX_Video:RX_Video_1|RX_Toggle is being clocked by CLK_50_Bank7ACLK_50_Bank7A is the input clock feeding the PLLs, where a couple are used to created clocks that are muxed onto HDMI_TX_CLK.In the design Register RX_Video:RX_Video_1|RX_Toggle is being clocked by another clock that are muxed in the same way as HDMI_TX_CLK.

Many thanks for your reply.Second attempt at posting!I haven't made any changes to the Assignment Editor, but deleted/renamed the old sdc file and created a new one from Timing Analyzer.These are now the active lines in the sdc file:**************************************************************create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]create_clock -name {HDMI_TX_CLK} -period 6.750 -waveform { 0.000 3.375 } [get_ports {HDMI_TX_CLK}]set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a*}]set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a*}]set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_hd9:dffpipe19|dffe20a*}]set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_gd9:dffpipe13|dffe14a*}]set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_rd9:dffpipe8|dffe9a*}]set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_qd9:dffpipe5|dffe6a*}]set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_pd9:dffpipe8|dffe9a*}]set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_od9:dffpipe5|dffe6a*}]**************************************************************After compiling the design which fitted fine and very quickly, I reopened Timing Analyzer, "Read the SDC File", double clicked "Report Setup Summary" and got a single line:altera_reserved_tck 7.788 0.000There was no line in the table indicating HDMI_TX_CLKI am using SignalTap where the clock is also the missing clock HDMI_TX_CLK. SignalTap works as expected. The fitter report says it found "2 clocks" consistent with the SDC file. There are some expected warnings from not specifying the periods of input clocks that are specified in PLLs.One thing that bothers me is this line and is mentioned 5 times in the processing messages: Info (13166): Register RX_Video:RX_Video_1|RX_Toggle is being clocked by CLK_50_Bank7ACLK_50_Bank7A is the input clock feeding the PLLs, where a couple are used to create 4 clocks that are muxed onto HDMI_TX_CLK.In the design Register RX_Video:RX_Video_1|RX_Toggle is being clocked by a clock that selected from1 of 4 clocked the same way HDMI_TX_CLK is created.

So HDMI_TX_CLK is an output clock you are creating and you say it is being used to clock internal logic as well?Run Report Clocks, not a setup summary, to verify clocks in your design. If it's not showing up in setup summary, that means it's not clocking anything internally.

Many thanks.The "Report Clocks" does list this clock as I would expect.HDMI_TX_CLK, or some variant of it, is clocking a lot of logic other pins are dependent on this and are behaving as expected. The same signal is used throughout the design so how can I check that setup and hold times aren't violated?

Clock missing from Timing Analyzer - Report Setup Summary

32 Replies

ShengN_altera
Super Contributor
2 years ago
Hi,

May I know does your problem resolved ady?

Thanks,
Regards,
Sheng
- Mikexx
  Occasional Contributor
  2 years ago
  The issue is not resolved.
  The HDMI_TX_CLK clock is present in Timing Analyzer->
  Diagnostic-> Report Clocks
  Diagnostic-> Report Clock Tree
  Diagnostic-> Report SDC
  but not in any other category. Not even Datasheet->Report Fmax Summary
ShengN_altera
Super Contributor
2 years ago
Possible to provide design for taking a look? May be can provide personally to my working email address.
- Mikexx
  Occasional Contributor
  2 years ago
  Many thanks for the offer. I have made some changes but still have the underlying problem. I have cut down the design by removing Signal tap etc that is now emailable in a small zip.
  I've looked at you profile but I can't see any contact details or any means to email you with the design.
  Can you assist?
ShengN_altera
Super Contributor
2 years ago
Here is my working email qi.sheng.ng@intel.com
- Mikexx
  Occasional Contributor
  2 years ago
  Many thanks for your kind offer.
  I sent an email of a zipped design that has been cut down to exclude items like SignalTap that take up an extraordinary amount of disk space. I can confirm this compiles and shows the issues.
  Now it's fingers crossed on how aggressive the Intel email filters are!
ShengN_altera
Super Contributor
2 years ago
Hi,

I didn't receive the design file. Could you provide the design file to me through drive link?
ShengN_altera
Super Contributor
2 years ago
Hi,
I had checked the design. Since HDMI_TX_CLK is not source-synchronous, so you wouldn't see the setup and hold.
You can report the delay by Report Path... From put * and To put [get_keepers {HDMI_TX_CLK}] then you'll see the result like below:
Thanks,
Regards,
Sheng
- Mikexx
  Occasional Contributor
  2 years ago
  Many thanks for looking into this. And apologies for the delay due to personal commitments.
  I'm a little confused as other clock signals are global and also generated from a PLL and yet are listed in the setup and old times.
  My understanding of a source synchronous system is when the signal source is clocked by a different clock to the destination register?
  The design has many registers that are clocked by a global clock, ie a common clock, in this case HDMI_TX_CLK aka TX_PCLK and therefore should all have a common clock topology?
ShengN_altera
Super Contributor
2 years ago
Hi,

HDMI_TX_CLK is an output clock. The timing analyzer does not automatically include them in the internal setup timing analysis unless there is a specific output delay constraint.
Without an explicit constraint, the tool may not consider the output clock when analyzing internal data paths since it assumes the clock is external and isn't used for internal synchronization.
By applying source synchronous output constraint (ie. set_output_delay), you effectively guide the timing analyzer to check that the data arrives at the output in sync with HDMI_TX_CLK, and the required setup and hold times are met. As a result, HDMI_TX_CLK will appear in the setup report since it now plays a crucial role in determining whether the output timing meets your design's requirements.

You may check this link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/exm-tq-ea-ss-out.html for an example of source synchronous output constraint. There're more details in document AN433.

Thanks,
Regards,
Sheng
- Mikexx
  Occasional Contributor
  2 years ago
  As explained I had changed the design in the design file I gave you such there was an internal clock signal TX_PCLK that went through an IO buffer in an attempt to separate the pin signal HDMI_TX_CLK and the internal clock.
  TX_PCLK is what was the old HDMI_TX_CLK. Sorry for any confusion.
ShengN_altera
Super Contributor
2 years ago
Hi,

TX_PCLK is a net. In.sdc, you have to use get_nets
create_clock -name {TX_PCLK} -period 6.734 -waveform { 0.000 3.367 } [get_nets {TX_PCLK}]

Thanks,
Regards,
Sheng
- Mikexx
  Occasional Contributor
  2 years ago
  Many thanks. Brill

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Clock missing from Timing Analyzer - Report Setup Summary

32 Replies

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