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Altera_Forum
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16 years ago

Cascading PLLs in Stratix-III

Hi,

I'm trying to feed inclk0 of one PLL from the output of a different PLL. The Stratix-III device handbook implies that you can drive inclk0 from GCLK network (see Table 6-2) but Quartus gives me an error saying it must be an I/O pin.

I have checked the fitter resource report and the output of the first PLL is clearly on a global network.

Any ideas ?

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Here is more background:

Design receives 24 MHz and spins it up to 96 MHz for most internal logic, with "sys_pll".

Design interfaces to external synchronous SRAM at 96 MHz. Desire to use PLL in external clock feedback mode, to equalize off-chip clock delays.

1. In external clock feedback mode, since fbout is driven by M counter, I need to have inclk0 and fbout frequency the same. So I can't spin 24->96 MHz in one PLL.

2. So I tried to use a 2nd PLL which receives internal global 96 MHz and creates a compensated 96 MHz to drive off-chip. The PCB has trace-length matched route back to fbin to compensate for clock delay to external SRAM.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Well I just did a little test compile with cascaded PLLs and it worked fine. I suspect your problem is this (from page 6-28 of the Stratix III device handbook):

    --- Quote Start ---

    The input and output delays are fully compensated by a PLL only when they are

    using the dedicated clock input pins associated with a given PLL as the clock source.

    Input and output delays are not compensated when cascading two adjacent top or

    bottom PLLs even if they are using dedicated routing for cascading. For example,

    when using PLL_T1 in normal mode, the clock delays from the input pin to the PLL

    clock output-to-destination register are fully compensated provided the clock input

    pin is one of the following four pins: CLK12, CLK13, CLK14, or CLK15. When an

    RCLK or GCLK network drives the PLL, the input and output delays may not be fully

    compensated in the Quartus II software.

    --- Quote End ---

    If you are trying to force the second PLL to do feedback compensation, it is wanting the clock input to be on an input pin.

    Jake