Arria10 HPS IP File missing

Hi,

I do not get any template or GHRD to generate HDL in Plattform Designer, because the IP for the HPS are missing.

Can anyone provide me a complete GHRD project for 25.1.1 for the Arria 10 SoC Development Kit ?

It would be nice to already have 1 Bit from Linux matched to one Output pin on the FPGA and one Input Pin on the FPGA to call from Linux.

That would be so nice and stop my odyssey

Thanx to the one out there who can send me such a Project.

Have a nice evenig.

Greez Linus

Hello,

today I spend the hole day to generate a Project out of the GHRD and all worked well and I thought this time it is korrekt.

But when I finished there was again no IP for the HPS......

Here is an Tutorial how to generate a Project out of the GHRD.

Maybe it helps someone:

Generate Quartus Project from a10_soc_devkit_ghrd_pro

Downloadlink:
https://github.com/altera-opensource/ghrd-socfpga

Die generierten *.qsys dateien werden in Benutzerverzeichnis der PCs geschoben!!!
Können aber manuell nach dem ersten generieren in den HauptProjekt Ordner kopiert werden.

den Ordner:a10_soc_devkit_ghrd_pro
kopieren ins Projekt Verzeichnis:

L:\LGP\Projects\DLR_C10303\DLR_BSR_Modem_FPGA_P2254\Dokumentation\Software\FPGA\FPGA_BSR_Projects\BSRFPGA_SW_V13\ghrd-socfpga-master\a10_soc_devkit_ghrd_pro

Im File: create_ghrd_qsys.tcl im Ordner: a10_soc_devkit_ghrd_pro

ganz oben statt "#source ./design_config.tcl" einfügen:

#______________________________________________________________________
# Eingefügt LGr 20250917:

# Kommandozeilenparameter übernehmen
if {[info exists ::argv]} {
foreach {param value} $::argv {
if {[string match "device*" $param]} {set device $value}
if {[string match "board_rev*" $param]} {set board_rev $value}
if {[string match "hps_sdram*" $param]} {set hps_sdram $value}
}
}

# Quartus Qsys-Pfade hinzufügen
lappend auto_path "C:/altera_pro/25.1.1/quartus/sopc_builder/lib"

# Absolutes Projektverzeichnis setzen
set project_dir "Dein Projekt Ordner Pfad z.B.: C:/MeineProjecte/Projects/a10_soc_devkit_ghrd_pro"

# Arbeitsverzeichnis wechseln, damit ./ korrekt funktioniert
cd $project_dir

# design_config.tcl relativ zum Projektverzeichnis einbinden
set design_config_file [file join $project_dir "design_config.tcl"]
if {[file exists $design_config_file]} {
source $design_config_file
} else {
error "design_config.tcl konnte nicht gefunden werden: $design_config_file"
}

#______________________________________________________________________

Windows PowerShell:

# Quartus Bin in PATH einfügen
$env:PATH += ";C:\altera_pro\25.1.1\quartus\bin64"

# In das Projektverzeichnis wechseln
cd "Dein Projekt Ordner Pfad z.B.: "C:\MeineProjecte\Projects\a10_soc_devkit_ghrd_pro"

# GHRD Quartus Projekt erzeugen
quartus_sh --script=create_ghrd_quartus.tcl device=10AS066N3F40E2SG board_rev=C hps_sdram=D9WFH

# GHRD Top-Level erzeugen
quartus_sh --script=create_ghrd_top.tcl device=10AS066N3F40E2SG board_rev=C hps_sdram=D9WFH

Windows CMD:
C:\altera_pro\25.1.1\quartus\sopc_builder\bin\qsys-script.exe ^
--script="Dein Projekt Ordner Pfad z.B.: "C:\MeineProjecte\Projects\a10_soc_devkit_ghrd_pro\create_ghrd_qsys.tcl" ^
--cmd="set device 10AS066N3F40E2SG; set board_rev C; set hps_sdram D9WFH"

It so crazy, if I put in any other HPS from the IP-Cataloge to my system, beside of an a10_HPS, they have an IP-File, eaven I have not installed any of them.

See Pics attached.

Hi,

Sorry for the delay in response as I just got back to office, I tested on Quartus Pro Linux 25.1.1, 25.1 , 24.3, 23.3 and I can see the same behavior whereby IP file is listed as none for Arria 10.

I checked our internal database and saw there was a case note that mentions Arria 10 altera_arria10_hps ships the HPS content as .qsys hardware project file instead of .ip file (similar to older devices eg. Cyclone V). For newer devices such as Stratix 10 , Agilex 7 onwards, the approach is to ship the HPS as a modular IP component with separate HPS IP releases for Platform Designer instantiation.

Just FYI , there is Arria 10 GSRD user guide on generating the gsrd and other files

https://altera-fpga.github.io/rel-25.1.1/embedded-designs/arria-10/sx/soc/gsrd/ug-gsrd-a10sx-soc/#compiling-hardware-design

Note: for gsrd, the repo https://github.com/altera-opensource/gsrd-socfpga is no longer updated after 24.3, the new repo is this https://github.com/altera-fpga/arria10-ed-gsrd

(will be updated in the document)

Also discussed with our factory team to confirm that the warning(Warning message :- “Warning: File path could not be determined for component altera_arria10_hps in xxx.qsys. The component is ignored for generation.") could be safely ignored.

Anyway, I noticed that by disabling the Parallel IP generation, it will remove the warning message on the File path could not be determined.

Thanks.

Regards

Kian