New ContributorAltera Register Chain
Hello,
I'm a student at Georgia Tech. I want to do some timing analysis on flip-flop/register chains. I've read the relevant material for the two devices I have access to - a Cyclone 5 and a Stratix 4. But, even when I manually connect the registers together (top register's q port feeds the bottom register's d port) and constration location assignments, Quartus rearranges how this register works. Most of the time, the simulation is using the asdata port instead of the d port. Chip Planner also shows this transformation happening. This means, I can't actually do the timing analysis I'd like to do. Sometimes it will instead use a lut to feed the flip flop's d port. Both of these situations are ones I'm trying to avoid.
I've attempted using generate statements to generate arbitrary shift registers and randomly used logic, but I'm guessing the fan-out is too low to force the router to use the register chain. There's very little information on this feature that's been advertised in multiple devices. I've found one other forum thread about this from 2010, but it didn't really solve anything.
Could a moderator provide clarification or a design for the Stratix 4 or Cyclone 5 that makes use the register chain? It's advertised, but I can't get it to synthesize.
