Forum Discussion

druepy's avatar
druepy
Icon for New Contributor rankNew Contributor
3 years ago

Altera Register Chain

Hello, I'm a student at Georgia Tech. I want to do some timing analysis on flip-flop/register chains. I've read the relevant material for the two devices I have access to - a Cyclone 5 and a Stratix...
Hdl
druepy's avatar
druepy
Icon for New Contributor rankNew Contributor
3 years ago

That's functionally what I'm trying to do.

The specifics are that I'm trying to avoid it using normal routing. The handbooks talk about register cascading. In Chip Planner, that should show a direct connection between the to FF in an ALM and the bottom FF in an alm.

I just did a quick glance at that first link you sent me. It mentions the cascade chains; I'm specifically trying to get a design that utilizes a cascade chain so I can measure the (likely minute) differences between the different methods Quartus uses to route. Are your modifications synthesizing a cascade chain?