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druepy's avatar
druepy
Icon for New Contributor rankNew Contributor
3 years ago

Altera Register Chain

Hello, I'm a student at Georgia Tech. I want to do some timing analysis on flip-flop/register chains. I've read the relevant material for the two devices I have access to - a Cyclone 5 and a Stratix...
Hdl
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Is this what you're trying to achieve with the design you shared?

I removed the location assignments set to reg_out* so it is able to run fitter- they're set too close to lc* signal locations so routing failed. If you don't want your registers to be retimed, setting location assignment is not the right way. Instead, you should use the Netlist Optimization setting to "Never Allow" : https://www.intel.com/content/www/us/en/docs/programmable/683230/18-1/preventing-register-movement-during-retiming.html

You may also find this useful: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir.htm

Regards,

Nurina