Altera Register Chain

Hello,

I called it register chaining, but it appears the datasheet calls it register cascading.

My approach has been to exhaust local system resources to force Quartus to have to utilize the register cascade connection.

I've tried a few different approaches. One approach is to use extended_lut's to use the majority of the ALM inputs to prevent Quartus from being able to utilize the connections to ASDATA. I combined this with an exclusion_list in the rcf. This caused a fitting error.

I've also use Verilog Generate statements to force a ton of logic cells to be used as well as flip flops. That didn't show anything.

I then attempted the same thing, but with ALM's that use the adder. This also had the same error. I searched our repository of designs and also didn't see this utilized anywhere; including some very resource intensive designs. I'm starting to think there's a bug in Quartus preventing this, but this hasn't been stated in the errata. It's also very heavily advertised for multiple chips, so I'm unsure why it's so difficult to get Quartus to do this.

I've attached my qar file. I appreciate the help.