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Altera_Forum
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14 years ago

Altera library missing- Modelsim

Hello All, I have built a system on Altera DSP builder and sucessfully exported to VHDL files to bring it on Quartus II. I need to run Powerplayanalysis, for that .vcd file needs to be generated ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You could use the TestBench block to generate a modelsim testbench or perhaps you could use the VCD Sink block to generate a VCD file directly in Simulink.