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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
8 days ago

agilex7 retiming restriction

my project has the following retiming restriction:

; Retiming Restrictions at Register #1: ;

; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~DUPLICATE ;

; due to the following restrictions: ;

; Register has either no inputs or output, and retiming for such nodes has been disabled

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Critical Chain Details ;

+--------------------------+-------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Path Info ; Register ; Register ID ; Element ;

+--------------------------+-------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Retiming Restriction ; Hyper-Register ; #1 ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~DUPLICATE_Duplicate ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~DUPLICATE_Duplicate|q ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~DUPLICATE~_BLOCK_INPUT_MUX_PASSTHROUGH_X208_Y237_N0_I11 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~DUPLICATE~_LAB_RE_X208_Y237_N0_I15 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn|datae ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn|combout ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_LAB_RE_X208_Y237_N0_I130 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C1_X208_Y237_N0_I8 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R1_X208_Y238_N0_I8 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R0_X207_Y238_N0_I14 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R0_X207_Y238_N0_I33 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R0_X207_Y238_N0_I69 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X207_Y230_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X207_Y222_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X207_Y214_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X207_Y206_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X207_Y198_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X207_Y190_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X207_Y182_N0_I2 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R0_X207_Y182_N0_I41 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R12_X196_Y182_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X195_Y174_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X195_Y166_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X195_Y158_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X195_Y150_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X195_Y142_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C8_X195_Y134_N0_I0 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R0_X195_Y134_N0_I2 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R1_X195_Y134_N0_I30 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R6_X189_Y134_N0_I17 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R6_X183_Y134_N0_I17 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R6_X177_Y134_N0_I17 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_C1_X176_Y133_N0_I35 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R1_X176_Y133_N0_I34 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_R1_X175_Y133_N0_I34 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_LOCAL_INTERCONNECT_X174_Y133_N0_I72 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_BLOCK_INPUT_MUX_PASSTHROUGH_X174_Y133_N0_I80 ;

; Long Path (Critical) ; ; ; x_quartus_hyperpipe_rst_clk_fb_pipe|GEN_REG_INPUT.R_data[7][0]~xsyn~_LAB_RE_X174_Y133_N0_I82 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_fb|x_tdb|x_stream_buff_pkt_fifo|x_stream_buff_ctl|x_scfifo|auto_generated|dpfifo|rd_ptr_msb|count[0]~xtophalf/xale3/xcw_la_le_regctrl/xcw_la_le_regctrl_reg/sclr_out ;

; Long Path (Critical) ; ; ; x_blk_fb|x_tdb|x_stream_buff_pkt_fifo|x_stream_buff_ctl|x_scfifo|auto_generated|dpfifo|low_addressa[3]|sclr ;

; Long Path (Critical) ; ALM Register ; #2 ; x_blk_fb|x_tdb|x_stream_buff_pkt_fifo|x_stream_buff_ctl|x_scfifo|auto_generated|dpfifo|low_addressa[3]

how to fix the timing restriction?

 

Compilation

2 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 hours ago

    Do you able to resolve the retiming restriction? 
    Do you have further inquiries regarding this case?

    Regards,
    Richard Tan

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    6 days ago

    As indicated in the message, this retiming restriction occurs when the retimer has determined that a register has dangling connections, either its data input or output is unconnected or was optimized away.
    1. Try to add pipeline regsiter between the Hyperpipe and SCFIFO.
    Since the critical path is the physical distance between x_quartus_hyperpipe_rst_clk_fb_pipe and x_blk_fb|x_tdb|x_stream_buff_pkt_fifo, add explicit pipeline registers in your RTL at the boundary between these two modules.

    2. Try to run Fast Forward Compile to get the tool specific recommendation. 
    https://www.youtube.com/watch?v=2Sym26y3v7Y

    Perhaps sharing a simplified design .QAR will help for further debugging. 

    Regards,
    Richard Tan