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In my first implementation my slave logic asserts waitrequest asynchronously when selected (based on chipselect_n) and then de-asserts when my Slave has the data ready.
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That is generally never a good idea.
If your device can accept one transaction on the first clock, then just register the waitrequest output based on being selected.
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But in signal tap I see the chip select from the master never deasserts and the R/W hangs (using FS2 console the indication is that the CPU is hung).
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You should create an SOPC System with an Avalon-MM BFM and your component and debug it there.
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so my question is how can I assert waitrequest asynchronously (as the avalon spec shows) and then deassert it synchronously based on my logic?
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I am sure you can. However, you should not. Timing analysis, and meeting timing, is much simpler to achieve if you implement your slaves in one of two ways;
1) The slave is always ready (waitrequest low), and if it needs to, it asserts waitrequest after accepting the first command, and leaves it asserted until its ready for the next command, or
2) The slave is always not ready (waitrequest high), and when it is selected, it deasserts waitrequest for a clock to accept the transaction, and then it processes it.
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if (rst_n = '0') then
waitrequest = '0';
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A device that has a waitrequest signal should leave it asserted until after reset deasserts ... this is either in the spec, or its a warning that the Avalon-MM monitor generates ... I forget which.
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any ideas??
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Simulate in Modelsim. Use a statemachine to detect chipselect, and manipulate waitrequest, and to check when your logic is done.
If you don't know how to do any of this, ask, and I'll post an example.
Cheers,
Dave
Honored Contributor
