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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verify failed between adress xxxx and xxxx (corresponds to SSRAM adress)

Hi all,

I am using Cyclone III NEEK NIOS II development kit. I have created a project by using VIP suite components and drive the lcd on the board which has a resolution 800x480.

Then I want to drive another lcd which has resolution 800x600.I have used the same system which I have used for 800x480.Only changed the scaler part and clocked video output part according to 800x600 resolution. However when I have compiled the program in eclipse, I came across the problem which says "verify failed between adress xxxxx and xxxxxx". This adress map corresponds to ssram.

I couldn't understand why these error occurs. I have exactly using the same code as before. Code size is the same. I am using ssram for exception memory of cpu and .bss,.rodata,.rwdata,.heap,.stack and .text region as I have used in previos case. I did not see any error before, however now I see although there is no difference except the resolution.

What can be the reason for that error? Can anyone help me please?

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It could be a timing problem... do you have timing constraints for the SSRAM interface and does the design meet the timing requirements?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, I have changed. for 800*480 resolution my system was wrking in 100 MHZ clock domain which is three times of the pixel clock, since on neek board we are allowed to send pixel data by sequence. So in order to drive 800*600 lcd with 40 MHz pixel clock I have made the clock for cpu, ssram and flash 120 Mhz.

    Does this change make this error? I could not understand why.

    Also, Iwan to ask you one more question. In SOPC builder after we put the components we assign a clock to each component.This clock is used for what? I am asking this because for clocked video output component, I have made the SOPC builder clock 100 Mhz (for 800*480 sequence data).After generating the SOPC builder, and go to the hdl part; in the created sopc_inst.v file for clocked video output component there is a clock assignment one more time.What is the relationship between these clocks. I have drive that clock with 40 Mhz, then I could get the true sync signals.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Did you change this frequency in a pll component? Inside SOPC builder or outside?

    Are all your interface properly constrain and do you have any complain from Timequest about not meeting the timing requirements? Look in the critical warnings. 120MHz starts to be high for a Nios CPU on a Cyclone III. It's possible be requires to be very careful.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes I have changed this frequency in a pll component inside SOPC builder.I have looked at the critical timings but I could not understand anything about that issue:S I am not experienced in this area very much.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If your hardware is directly driving the LCD panel, the pixel clock rate isn't that important.

    When I was doing it (actually from an SA1100/1101 ARM system) at slow rates I saw some visual flicker (and odd/even frame differences).

    Very slow rates (frame rates < 1Hz) showed some interesting effects!.

    I ended up changing the pixel clock frequency on the fly (mid frame) in order to stop the video dma underrunning when the cpu was doing slow cycles on the shared bus.